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Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply TTL/CMOS Comparator ADCMP603
FEATURES
Fully specified rail to rail at VCC = 2.5 V to 5.5 V Input common-mode voltage from -0.2 V to VCC + 0.2 V Low glitch CMOS-/TTL-compatible output stage Complementary outputs 3.5 ns propagation delay 12 mW at 3.3 V Shutdown pin Single-pin control for programmable hysteresis and latch Power supply rejection > 50 dB -40C to +125C operation
FUNCTIONAL BLOCK DIAGRAM
VCCI VCCO
VP NONINVERTING INPUT
Q OUTPUT
ADCMP603
VN INVERTING INPUT
TTL Q OUTPUT
LE/HYS INPUT SDN INPUT
APPLICATIONS
High speed instrumentation Clock and data signal restoration Logic level shifting or translation Pulse spectroscopy High speed line receivers Threshold detection Peak and zero-crossing detectors High speed trigger circuitry Pulse-width modulators Current-/voltage-controlled oscillators Automatic test equipment (ATE)
Figure 1.
GENERAL DESCRIPTION
The ADCMP603 is a very fast comparator fabricated on XFCB2, an Analog Devices, Inc. proprietary process. This comparator is exceptionally versatile and easy to use. Features include an input range from VEE - 0.5 V to VCC + 0.2 V, low noise complementary TTL-/CMOS-compatible output drivers, latch inputs with adjustable hysteresis and a shutdown input. The device offers 3.5 ns propagation delay with 10 mV overdrive on 4 mA typical supply current. A flexible power supply scheme allows the device to operate with a single +2.5 V positive supply and a -0.5 V to +2.8 V input signal range up to a +5.5 V positive supply with a -0.5 V to +5.8 V input signal range. Split input/output supplies with no sequencing restrictions support a wide input signal range while still allowing independent output swing control and power savings. The device passes 4.5 kV HBM ESD testing and the absolute maximum ratings include current limits for all pins. The complementary TTL-/CMOS-compatible output stage is designed to drive up to 5 pF with full timing specs and to degrade in a graceful and linear fashion as additional capacitance is added. The comparator input stage offers robust protection against large input overdrive, and the outputs do not phase reverse when the valid input signal range is exceeded. Latch and programmable hysteresis features are also provided with a unique single-pin control option. The ADCMP603 is available in a 12-lead LFCSP package.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved.
05915-001
ADCMP603 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Electrical Characteristics............................................................. 3 Timing Information ......................................................................... 5 Absolute Maximum Ratings............................................................ 6 Thermal Resistance ...................................................................... 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ............................................. 8 Application Information................................................................ 10 Power/Ground Layout and Bypassing..................................... 10 TTL-/CMOS-Compatible Output Stage ................................. 10 Using/Disabling the Latch Feature........................................... 10 Optimizing Performance........................................................... 11 Comparator Propagation Delay Dispersion ........................... 11 Comparator Hysteresis .............................................................. 11 Crossover Bias Point .................................................................. 12 Minimum Input Slew Rate Requirement ................................ 12 Typical Application Circuits ......................................................... 13 Outline Dimensions ....................................................................... 14 Ordering Guide .......................................................................... 14
REVISION HISTORY
10/06--Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADCMP603 SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VCCI = VCCO = 2.5 V, TA = 25C, unless otherwise noted. Table 1.
Parameter DC INPUT CHARACTERISTICS Voltage Range Common-Mode Range Differential Voltage Offset Voltage Bias Current Offset Current Capacitance Resistance, Differential Mode Resistance, Common Mode Active Gain Common-Mode Rejection Ratio Symbol VP, VN Conditions VCC = 2.5 V to 5.5 V VCC = 2.5 V to 5.5 V VCC = 2.5 V to 5.5 V Min -0.5 -0.2 -5.0 -5.0 -2.0 -0.5 V to VCC + 0.2 V -0.2 V to VCC + 0.2 V AV CMRR VCCI = 2.5 V, VCCO = 2.5 V, VCM = -0.2 V to +2.7 V VCCI = 5.5 V, VCCO = 5.5 V, VCM = -0.2 V to +5.7 V RHYS = Hysteresis is shut off Latch mode guaranteed VIH = VCC VIL = 0.4 V Current sink -1 A Hysteresis = 120 mV Hysteresis = 120 mV VOD = 50 mV VOD = 50 mV VOD = 50 mV VOD = 50 mV Comparator is operating Shutdown guaranteed VIH = VCC VIL = 0 V IOUT < 0.5 mA VOD = 100 mV, output valid VCCO = 2.5 V to 5.5 V IOH = 8 mA VCCO = 2.5 V IOH = 6 mA VCCO = 2.5 V IOL = 8 mA, VCCO = 2.5 V IOL = 6 mA, VCCO = 2.5 V 200 100 50 50 0.1 2.0 -0.2 -6 VCC +0.8 +6 -0.1 1.35 95 -10 VCC + 0.8 2 2 1.0 700 350 85 Typ Max VCC + 0.2 VCC + 0.2 +5.0 +5.0 2.0 Unit V V V mV A A pF k k dB dB dB mV V V A mA V k A ns ns ns ns V V A A ns ns V V V V
VOS IP, IN CP, CN
Hysteresis LATCH ENABLE PIN CHARACTERISTICS VIH VIL IIH IOL HYSTERESIS MODE AND TIMING Hysteresis Mode Bias Voltage Resistor Value Hysteresis Current Latch Setup Time Latch Hold Time Latch-to-Output Delay Latch Minimum Pulse Width SHUTDOWN PIN CHARACTERISTICS VIH VIL IIH IOL Sleep Time Wake-Up Time DC OUTPUT CHARACTERISTICS Output Voltage High Level Output Voltage High Level -40C Output Voltage Low Level Output Voltage Low Level -40C
+0.4
1.145 65 -18
tS tH tPLOH, tPLOL tPL
1.25 80 -14 -2.0 2.0 30 23
2.0 -0.2 -6
+0.4 -80 20 50
VCCO +0.6 +6
tSD tH VOH VOH VOL VOL
VCC - 0.4 VCC - 0.4 0.4 0.4
Rev. 0 | Page 3 of 16
ADCMP603
Parameter AC PERFORMANCE 1 Rise Time /Fall time Propagation Delay Symbol tR/tF tPD Conditions 10% to 90%, VCCO = 2.5 V 10% to 90%, VCCO = 5.5 V VOD = 50 mV, VCCO = 2.5 V VOD = 50 mV, VCCO = 5.5 V VOD = 10 mV, VCCO = 2.5 V VCCO = 2.5 V to 5.5 V VOD = 50 mV VCCO =2.5 V to 5.5 V VOD = 50 mV 10 mV < VOD < 125 mV -2 V < VCM < VCCI + 2 V VOD = 50 mV VCCI = VCCO = 2.5 V PWOUT = 90% of PWIN VCCI = VCCO = 5.5 V PWOUT = 90% of PWIN 2.5 2.5 -3.0 -5.5 1.1 2.3 9 21 -50 290 430 Min Typ 2.2 4.5 3.5 4.8 5 500 300 1.5 200 3.3 5.5 Max Unit ns ns ns ns ns ps ps ns ps ns ns
Propagation Delay Skew--Rising to Falling Transition Propagation Delay Skew--Q to QB Overdrive Dispersion Common-Mode Dispersion Minimum Pulse Width
tPINSKEW tDIFFSKEW
PWMIN
POWER SUPPLY Input Supply Voltage Range Output Supply Voltage Range Positive Supply Differential Positive Supply Differential Input Section Supply Current Output Section Supply Current Power Dissipation Power Supply Rejection Ratio Shutdown Mode Supply Current
1
VCCI VCCO VCCI - VCCO VCCI - VCCO IVCCI IVCCO PD PD PSRR
Operating Nonoperating VCCI = 2.5 V to 5.5 V VCCI = 2.5 V to 5.5 V VCC = 2.5 V VCC = 5.5 V VCCI = 2.5 V to 5.5 V VCC =2.5 V
5.5 5.5 +3.0 +5.5 1.8 3.5 11 30
V V V V mA mA mW mW dB A
VIN = 100 mV square input at 50 MHz, VCM = 0 V, CL = 5 pF, VCCI = VCCO = 2.5 V, unless otherwise noted.
Rev. 0 | Page 4 of 16
ADCMP603 TIMING INFORMATION
Figure 2 illustrates the ADCMP603 latch timing relationships. Table 2 provides definitions of the terms shown in Figure 2.
1.1V LATCH ENABLE
tS tH
tPL
DIFFERENTIAL INPUT VOLTAGE
VIN VOD
VN VOS
tPDL
Q OUTPUT
tPLOH
50%
tPDH
tF
50%
Q OUTPUT
tR
Figure 2. System Timing Diagram
Table 2. Timing Descriptions
Symbol tPDH tPDL tPLOH tPLOL tH tPL tS tR tF VOD Timing Input to output high delay Input to output low delay Latch enable to output high delay Latch enable to output low delay Minimum hold time Minimum latch enable pulse width Minimum setup time Output rise time Output fall time Voltage overdrive Description Propagation delay measured from the time the input signal crosses the reference ( the input offset voltage) to the 50% point of an output low-to-high transition. Propagation delay measured from the time the input signal crosses the reference ( the input offset voltage) to the 50% point of an output high-to-low transition. Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output low-to-high transition. Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output high-to-low transition. Minimum time after the negative transition of the latch enable signal that the input signal must remain unchanged to be acquired and held at the outputs. Minimum time that the latch enable signal must be high to acquire an input signal change. Minimum time before the negative transition of the latch enable signal occurs that an input signal change must be present to be acquired and held at the outputs. Amount of time required to transition from a low to a high output as measured at the 20% and 80% points. Amount of time required to transition from a high to a low output as measured at the 20% and 80% points. Difference between the input voltages VA and VB.
Rev. 0 | Page 5 of 16
05915-023
tPLOL
ADCMP603 ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Supply Voltages Input Supply Voltage (VCCI to GND) Output Supply Voltage (VCCO to GND) Positive Supply Differential (VCCI - VCCO) Input Voltages Input Voltage Differential Input Voltage Maximum Input/Output Current Shutdown Control Pin Applied Voltage (HYS to GND) Maximum Input/Output Current Latch/Hysteresis Control Pin Applied Voltage (HYS to GND) Maximum Input/Output Current Output Current Temperature Operating Temperature, Ambient Operating Temperature, Junction Storage Temperature Range Rating -0.5 V to +6.0 V -0.5 V to +6.0 V -6.0 V to +6.0 V
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL RESISTANCE
-0.5 V to VCCI + 0.5 V (VCCI + 0.5 V) 50 mA -0.5 V to VCCO + 0.5 V 50 mA -0.5 V to VCCO + 0.5 V 50 mA 50 mA -40C to +125C 150C -65C to +150C
JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4. Thermal Resistance
Package Type ADCMP603 LFCSP 12-lead
1
JA1 62
Unit C/W
Measurement in still air.
ESD CAUTION
Rev. 0 | Page 6 of 16
ADCMP603 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
11 VEE 12 Q
VCCO 1 VCCI 2 VEE 3
PIN 1 INDICATOR
10 Q
ADCMP603
TOP VIEW (Not to Scale)
9 VEE 8 LE/HYS 7 SDN
Figure 3. ADCMP603 Pin Configuration
Table 5. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 Mnemonic VCCO VCCI VEE VP VEE VN SDN LE/HYS VEE Q Description Output Section Supply. Input Section Supply. Negative Supply Voltage. Noninverting Analog Input. Negative Supply Voltage. Inverting Analog Input. Shutdown. Drive this pin low to shut down the device. Latch/Hysteresis Control. Bias with resistor or current for hysteresis adjustment; drive low to latch. Negative Supply Voltage. Inverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN, if the comparator is in compare mode. See the LE/HYS pin description (Pin 8) for more information. Negative Supply Voltage. Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN, if the comparator is in compare mode. See the LE pin description (Pin 8) for more information. The metallic back surface of the package is electrically connected to VEE. It can be left floating because Pin 3, Pin 5, Pin 9, and Pin 11 provide adequate electrical connection. It can also be soldered to the application board if improved thermal and/or mechanical stability is desired. Exposed metal at package corners is connected to the heat sink paddle.
11 12
VEE Q
Heat Sink Paddle
VEE
Rev. 0 | Page 7 of 16
VEE 5
05915-002
VN 6
VP 4
ADCMP603 TYPICAL PERFORMANCE CHARACTERISTICS
VCCI = VCCO = 2.5 V, TA = 25C, unless otherwise noted.
800 600 400
CURRENT (A) TYPICAL OUTPUT VOLTAGE (V) 4
VCC = 2.5V
VCC = 5.5V
3
200 0 -200 -400
05915-007
2
1
0
OUTPUT VOLTAGE
-800 -1 0 1 2 3 4 5 LE/HYSTERESIS PIN VOLTAGE (V) 6 7
-2 -5
0
5
10
15
20
LOAD CURRENT (mA)
Figure 4. LE/HYS Pin I/V Curve
Figure 7. VOL vs. Load Current
200 150 100
CURRENT (A)
1000
VCC = 5.5V
HYSTERESIS (mV)
VCC = 2.5V
100 VCC = 5.5V
50 0 -50 -100 -150 -1
VCC = 2.5V 10
05915-006
0
1 2 3 4 5 SHUTDOWN PIN VOLTAGE (V)
6
7
1 50
150
250 350 450 HYSTERESIS RESISTOR (k)
550
650
Figure 5. SDN Pin I/V Curve
Figure 8. Hysteresis vs. RHYS
20 15
VCC = 2.5V
IB @ +125C IB @ +25C
350 300 250
HYSTERESIS @ +125C
10 5
IB (A)
IB @ -40C
HYSTERESIS (mV)
200 HYSTERESIS @ +25C 150 100 50 HYSTERESIS @ -40C 0 0 -2 -4 -6 -8 -10 -12 -14 -16 -18
0 -5 -10
05915-005
-20 -1.0
-0.5
0
0.5 1.0 1.5 2.0 2.5 COMMON-MODE VOLTAGE (V)
3.0
3.5
HYSTERESIS PIN CURRENT (A)
Figure 6. Input Bias Current vs. Input Common Mode
Figure 9. Hysteresis vs. Hysteresis Pin Current
Rev. 0 | Page 8 of 16
05915-003
-15
05915-004
05915-010
-600
-1
ADCMP603
8
7
PROPAGATION DELAY (ns)
6
5
4
3
05915-009 05915-024
2
0
10
20
30
40
50
60
70
80
90 100 110 120 130 140
OVERDRIVE (mV)
500mV/DIV
M2.00ns
Figure 10. Propagation Delay vs. Input Overdrive
4.0 VCC = 2.5V 3.8
Figure 12. 50 MHz Output Voltage Waveform at VCCO = 2.5 V
DELAY (ns)
3.6 PROP DELAY RISE ns 3.4 PROP DELAY FALL ns 3.2
05915-008
3.0 -0.6
0
0.6 1.2 1.8 COMMON-MODE VOLTAGE (V)
2.4
3.0
1.00V/DIV
M2.00ns
Figure 11. Propagation Delay vs. Input Common Mode
Figure 13. 50 MHz Output Voltage Waveform at VCCO = 5.5 V
Rev. 0 | Page 9 of 16
05915-025
ADCMP603 APPLICATION INFORMATION
POWER/GROUND LAYOUT AND BYPASSING
The ADCMP603 comparator is a very high speed device. Despite the low noise output stage, it is essential to use proper high speed design techniques to achieve the specified performance. Because comparators are uncompensated amplifiers, feedback in any phase relationship is likely to cause oscillations or undesired hysteresis. Of critical importance is the use of low impedance supply planes, particularly the output supply plane (VCCO) and the ground plane (GND). Individual supply planes are recommended as part of a multilayer board. Providing the lowest inductance return path for switching currents ensures the best possible performance in the target application. It is also important to adequately bypass the input and output supplies. Multiple high quality 0.01 F bypass capacitors should be placed as close as possible to each of the VCCI and VCCO supply pins and should be connected to the GND plane with redundant vias. At least one of these should be placed to provide a physically short return path for output currents flowing back from ground to the VCCO pin. High frequency bypass capacitors should be carefully selected for minimum inductance and ESR. Parasitic layout inductance should also be strictly controlled to maximize the effectiveness of the bypass at high frequencies. If the input and output supplies have been connected separately such that VCCI VCCO, care should be taken to bypass each of these supplies separately to the GND plane. A bypass between them is futile and defeats the purpose of having separate pins. It is recommended that the GND plane separate the VCCI and VCCO planes when the circuit board layout is designed to minimize coupling between the two supplies and to take advantage of the additional bypass capacitance from each respective supply to the ground plane. This enhances the performance when split input/output supplies are used. If the input and output supplies are connected together for single-supply operation such that VCCI = VCCO, coupling between the two supplies is unavoidable; however, careful board placement can help keep output return currents away from the inputs. This delay is measured to the 50% point for the supply in use; therefore, the fastest times are observed with the VCC supply at 2.5 V, and larger values are observed when driving loads that switch at other levels. When duty cycle accuracy is critical, the logic being driven should switch at 50% of VCC and load capacitance should be minimized. When in doubt, it is best to power VCCO or the entire device from the logic supply and rely on the input PSRR and CMRR to reject noise. Overdrive and input slew rate dispersions are not significantly affected by output loading and VCC variations. The TTL-/CMOS-compatible output stage is shown in the simplified schematic diagram (Figure 14). Because of its inherent symmetry and generally good behavior, this output stage is readily adaptable for driving various filters and other unusual loads.
VLOGIC
A1
Q1
+IN -IN AV
OUTPUT
A2
Q2
05915-012
GAIN STAGE
OUTPUT STAGE
Figure 14. Simplified Schematic Diagram of TTL-/CMOS-Compatible Output Stage
USING/DISABLING THE LATCH FEATURE
The latch input is designed for maximum versatility. It can safely be left floating for fixed hysteresis or be tied to VCC to remove the hysteresis, or it can be driven low by any standard TTL/CMOS device as a high speed latch. In addition, the pin can be operated as a hysteresis control pin with a bias voltage of 1.25 V nominal and an input resistance of approximately 7000 , allowing the comparator hysteresis to be easily controlled by either a resistor or an inexpensive CMOS DAC. Hysteresis control and latch mode can be used together if an open drain, an open collector, or a three-state driver is connected parallel to the hysteresis control resistor or current source. Due to the programmable hysteresis feature, the logic threshold of the latch pin is approximately 1.1 V regardless of VCC.
TTL-/CMOS-COMPATIBLE OUTPUT STAGE
Specified propagation delay performance can be achieved only by keeping the capacitive load at or below the specified minimums. The low skew complementary outputs of the ADCMP603 are designed to directly drive one Schottky TTL or three low power Schottky TTL loads or the equivalent. For large fan outputs, buses, or transmission lines, use an appropriate buffer to maintain the excellent speed and stability of the comparator. With the rated 5 pF load capacitance applied, more than half of the total device propagation delay is output stage slew time, even at 2.5 V VCC. Because of this, the total prop delay decreases as VCCO decreases, and instability in the power supply may appear as excess delay dispersion.
Rev. 0 | Page 10 of 16
ADCMP603
OPTIMIZING PERFORMANCE
As with any high speed comparator, proper design and layout techniques are essential for obtaining the specified performance. Stray capacitance, inductance, inductive power and ground impedances, or other layout issues can severely limit performance and often cause oscillation. Large discontinuities along input and output transmission lines can also limit the specified pulsewidth dispersion performance. The source impedance should be minimized as much as is practicable. High source impedance, in combination with the parasitic input capacitance of the comparator, causes an undesirable degradation in bandwidth at the input, thus degrading the overall response. Thermal noise from large resistances can easily cause extra jitter with slowly slewing input signals; higher impedances encourage undesired coupling.
INPUT VOLTAGE 1V/ns VN VOS 10V/ns
Q/Q OUTPUT
Figure 16. Propagation Delay--Slew Rate Dispersion
COMPARATOR HYSTERESIS
The addition of hysteresis to a comparator is often desirable in a noisy environment, or when the differential input amplitudes are relatively small or slow moving. Figure 17 shows the transfer function for a comparator with hysteresis. As the input voltage approaches the threshold (0.0 V, in this example) from below the threshold region in a positive direction, the comparator switches from low to high when the input crosses +VH/2, and the new switching threshold becomes -VH/2. The comparator remains in the high state until the new threshold, -VH/2, is crossed from below the threshold region in a negative direction. In this manner, noise or feedback output signals centered on 0.0 V input cannot cause the comparator to switch states unless it exceeds the region bounded by VH/2.
OUTPUT
COMPARATOR PROPAGATION DELAY DISPERSION
The ADCMP603 comparator is designed to reduce propagation delay dispersion over a wide input overdrive range of 5 mV to VCCI - 1 V. Propagation delay dispersion is the variation in propagation delay that results from a change in the degree of overdrive or slew rate (that is, how far or how fast the input signal exceeds the switching threshold). Propagation delay dispersion is a specification that becomes important in high speed, time-critical applications, such as data communication, automatic test and measurement, and instrumentation. It is also important in event-driven applications, such as pulse spectroscopy, nuclear instrumentation, and medical imaging. Dispersion is defined as the variation in propagation delay as the input overdrive conditions are changed (Figure 15 and Figure 16). ADCMP603 dispersion is typically < 2 ns as the overdrive varies from 10 mV to 125 mV. This specification applies to both positive and negative signals because the device has very closely matched delays for both positive-going and negative-going inputs.
500mV OVERDRIVE
VOH
VOL
-VH 2
0
+VH 2
Figure 17. Comparator Hysteresis Transfer Function
INPUT VOLTAGE 10mV OVERDRIVE VN VOS
Q/Q OUTPUT
Figure 15. Propagation Delay--Overdrive Dispersion
05915-013
DISPERSION
The customary technique for introducing hysteresis into a comparator uses positive feedback from the output back to the input. One limitation of this approach is that the amount of hysteresis varies with the output logic levels, resulting in hysteresis that is not symmetric about the threshold. The external feedback network can also introduce significant parasitics that reduce high speed performance and induce oscillation in some cases.
Rev. 0 | Page 11 of 16
05915-015
INPUT
05915-014
DISPERSION
ADCMP603
The ADCMP603 comparator offers a programmable hysteresis feature that can significantly improve accuracy and stability. Connecting an external pull-down resistor or a current source from the LE/HYS pin to GND varies the amount of hysteresis in a predictable, stable manner. Leaving the LE/HYS pin disconnected or driving it high removes the hysteresis. The maximum hysteresis that can be applied using this pin is approximately 160 mV. Figure 18 illustrates the amount of hysteresis applied as a function of the external resistor value, and Figure 9 illustrates hysteresis as a function of the current. The hysteresis control pin appears as a 1.25 V bias voltage seen through a series resistance of 7 k 20% throughout the hysteresis control range. The advantages of applying hysteresis in this manner are improved accuracy, improved stability, reduced component count, and maximum versatility. An external bypass capacitor is not recommended on the HYS pin because it impairs the latch function and often degrades the jitter performance of the device. As described in the Using/Disabling the Latch Feature section, hysteresis control need not compromise the latch function.
1000
HYSTERESIS (mV)
100 VCC = 5.5V
VCC = 2.5V 10
1 50
150
250 350 450 HYSTERESIS RESISTOR (k)
550
650
Figure 18. Hysteresis vs. RHYS Control Resistor
MINIMUM INPUT SLEW RATE REQUIREMENT
With the rated load capacitance and normal good PC Board design practice, as discussed in the Optimizing Performance section, these comparators should be stable at any input slew rate with no hysteresis. Broadband noise from the input stage is observed in place of the violent chattering seen with most other high speed comparators. With additional capacitive loading or poor bypassing, more persistent oscillations are seen. This oscillation is due to the high gain bandwidth of the comparator in combination with feedback parasitics in the package and PC board. In many applications, chattering is not harmful since the first cycle of the oscillation occurs close to VOS.
CROSSOVER BIAS POINT
In both op amps and comparators, rail-to-rail inputs of this type have a dual front-end design. Certain devices are active near the VCC rail and others are active near the VEE rail. At some predetermined point in the common-mode range, a crossover occurs. At this point, typically VCC/2, the direction of the bias current reverses and the measured offset voltages and currents change. The ADCMP603 slightly elaborates on this scheme. Crossover points can be found at approximately 0.8 V and 1.6 V.
Rev. 0 | Page 12 of 16
05915-026
ADCMP603 TYPICAL APPLICATION CIRCUITS
5V
2.5V TO 5V 0.1F INPUT 2k
INPUT
10k
+ OUTPUT -
05915-020
ADCMP603
2k
0.02F 10k
ADCMP603
CMOS OUTPUT
05915-017
VREF 0.1F LE/HYS
0.1F
Figure 19. Self-Biased, 50% Slicer
Figure 22. Duty Cycle to Differential Voltage Converter
2.5V TO 5V
ADCMP603
CMOS VDD 2.5V TO 5V
DIGITAL INPUT
LVDS 100
ADCMP603
CMOS OUTPUT
05915-018
74 AHC 1G07
LE/HYS
HYSTERESIS CURRENT
10k
Figure 20. LVDS-to-CMOS Receiver
Figure 23. Hysteresis Adjustment with Latch
2.5V
ADCMP603
INPUT 1.25V 50mV
CMOS PWM OUTPUT
5V
10k
INPUT 1.25V REF 10k
10k
150pF
ADCMP603
LE/HYS
OUTPUT
ADCMP601
10k 82pF LE/HYS
05915-021
150k
150k
05915-019
CONTROL VOLTAGE 0V TO 2.5V
10k
100k
Figure 21. Voltage-Controlled Oscillator
Figure 24. Oscillator and Pulse-Width Modulator
Rev. 0 | Page 13 of 16
05915-022
ADCMP603
2
OUTLINE DIMENSIONS
3.00 BSC SQ 0.45 PIN 1 INDICATOR TOP VIEW 2.75 BSC SQ EXPOSED PAD (BOTTOM VIEW) 12 MAX 1.00 0.85 0.80 SEATING PLANE 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08 0.50 BSC 0.60 MAX 0.75 0.55 0.35 PIN 1 INDICATOR *1.45 1.30 SQ 1.15
9 8 7
10
11 12
1 2
6
5
4
3
0.25 MIN
*COMPLIANT TO JEDEC STANDARDS MO-220-VEED-1 EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 25. 12-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 3 mm x 3 mm Body, Very Thin Quad (CP-12-1) Dimensions shown in millimeters
ORDERING GUIDE
Model ADCMP603BCPZ-WP1 ADCMP603BCPZ-R21 ADCMP603BCPZ-R71
1
Temperature Range -40C to +125C -40C to +125C -40C to +125C
Package Description 12-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 12-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 12-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Package Option CP-12-1 CP-12-1 CP-12-1
Branding G0D G0D G0D
Z = Pb-free part.
Rev. 0 | Page 14 of 16
ADCMP603 NOTES
Rev. 0 | Page 15 of 16
ADCMP603
2
NOTES
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05915-0-10/06(0)
Rev. 0 | Page 16 of 16

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